In contrast to conventional planar metal-oxide-semiconductor field-effect transistors (“MOSFETs”), multi-gate transistors incorporate two or more gates into a single device. Relative to single gate transistors, multi-gate transistors reduce off-state current leakage, increase on-state current flow, and reduce overall power consumption. Multi-gate devices having non-planar topographies also tend to be more compact than conventional planar transistors and consequently permit higher device densities to be achieved. One known type of non-planar, multi-gate transistor, commonly referred to as a “FinFET,” includes at least one fin structure formed on a substrate, such as a silicon-on-insulator substrate. The fin structure extends along a first axis between source and drain electrodes. At least one conductive gate stack is formed over the fin structure and extends along a second axis perpendicular to the first axis. More specifically, the gate stack extends across and over the fin structure such that an intermediate portion of the gate stack conformally overlays three surfaces of the fin structure (i.e., an upper surface, a first sidewall surface, and a second opposing sidewall surface of the fin structure).
It is well-established that the carrier mobility, and thus the switching speed, of a transistor can be significantly increased by applying a physically-deforming force (“stress”) to a transistor's channel region sufficient to induce a physical deformation (“strain”) within the silicon lattice. In the context of conventional planar transistors, stress can be applied to the channel region utilizing any one of a number of relatively straightforward straining techniques; e.g., in one common method, a strained layer of silicon nitride (Si3N4) is used as a contact etch stop and deposited over the final gate and source drain structure to apply a shear force thereto sufficient to induce strain within the channel region's crystal lattice; and, in another common method, a layer of silicon germanium (SiGe) is deposited in the source-drain region to apply a shear force thereto sufficient to induce strain within the channel region's crystal lattice. However, the unique topography of FinFETs and other non-planar semiconductor devices (e.g., triFETs) generally renders the implementation of conventional straining techniques excessively difficult. Even when it is practicable to utilize strain layers during the fabrication of a non-planar semiconductor device, any increase in carrier mobility improvement is typically limited; e.g., due to the lack of a confined source/drain, deposition of strained SiGe is predicted to result in a fraction (e.g., approximately half) of the carrier mobility achieved when similar straining techniques are utilized in conjunction with planar MOSFETs.
In view of the above, it is desirable to provide embodiments of a method for fabricating a non-planar semiconductor device, such as a FinFET, wherein stress memory is effectively imparted to one or more fin structures (or other raised crystalline structures) included within the non-planar semiconductor device. Ideally, embodiments of such a fabrication method would introduce strain directly to the fin structures through a multi-surface interface to optimize carrier mobility improvement. Other desirable features and characteristics of the present invention will become apparent from the subsequent Detailed Description and the appended Claims, taken in conjunction with the accompanying Drawings and this Background.